Memory Management
Q31.
Consider a system with byte-addressable memory, 32-bit logical addresses, 4 kilobyte page size and page table entries of 4 bytes each. The size of the page table in the system in megabytes is ________ .Q32.
What is the size of the physical address space in a paging system which has a page table containing 64 entries of 11 bit each (including valid and invalid bit) and a page size of 512 bytes?Q33.
A system uses 3 page frames for storing process pages in main memory. It uses the Least Recently Used (LRU) page replacement policy. Assume that all the page frames are initially empty. What is the total number of page faults that will occur while processing the page reference string given below? 4, 7, 6, 1, 7, 6, 1, 2, 7, 2Q34.
A computer has twenty physical page frames which contain pages numbered 101 through 120. Now a program accesses the pages numbered 1, 2, ..., 100 in that order, and repeats the access sequence THRICE. Which one of the following page replacement policies experiences the same number of page faults as the optimal page replacement policy for this program?Q35.
Assume that there are 3 page frames which are initially empty. If the page reference string 1, 2, 3, 4, 2, 1, 5, 3, 2, 4, 6, the number of page faults using the optimal replacement policy is ______Q36.
Consider a paging hardware with a TLB. Assume that the entire page table and all the pages are in the physical memory. It takes 10 milliseconds to search the TLB and 80 milliseconds to access the physical memory. If the TLB hit ratio is 0.6, the effective memory access time (in milliseconds) is _________.Q37.
Consider the list of page references in the time line as below: 9 6 2 3 4 4 4 4 3 4 4 2 5 8 6 8 5 5 3 2 3 3 9 6 2 7 What is the working set at the penultimate page reference if \Delta is 5?Q38.
Consider a logical address space of 8 pages of 1024 words each, mapped onto a physical memory of 32 frames. How many bits are there in the physical address and logical address respectively?Q39.
Consider the following segment table in segmentation scheme :\begin{array}{|l|l|l|} \hline \text { Segment ID } & \text { Base } & \text { Limit } \\ \hline 0 & 200 & 200 \\ \hline 1 & 5000 & 1210 \\ \hline 2 & 1527 & 498 \\ \hline 3 & 2500 & 50 \\ \hline \end{array}What happens if the logical address requested is - Segment Id 2 and offset 1000?Q40.
Using the page table shown below, translate the physical address 25 to virtual address. The address length is 16 bits and page size is 2048 words while the size of the physical memory is four frames.\begin{array}{lcc} \text { Page } & \text { Present }(1-In , 0-Out) & \text { Frame } \\ 0 & 1 & 3 \\ 1 & 1 & 2 \\ 2 & 1 & 0 \\ 3 & 0 & - \end{array}